1. Field of the Invention
The present invention generally relates to a nonvolatile ferroelectric memory cell and a memory device using the same, and more specifically, to a technology for storing processing results of various programs of a system in a nonvolatile ferroelectric register and inputting/outputting data stored in a cell through a multi port.
2. Description of the Prior Art
Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FeRAM’) has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a Dynamic Random Access Memory DRAM and conserves data even after the power is turned off.
The FeRAM having structures similar to the DRAM includes the capacitors made of a ferroelectric substance, so that it utilizes the characteristic of a high residual polarization of the ferroelectric substance in which data is not deleted even after an electric field is eliminated. The technical contents on the above FeRAM are disclosed in the Korean Patent Application No. 2002-85533 by the same inventor of the present invention. Therefore, the basic structure and the operation on the FeRAM are not described herein.
A central processing unit (CPU) comprising a control device, an operation device, an input/output device and a memory device performs an operation for data processing or controls data input/output operations. However, since the conventional CPU stores data based on a volatile SRAM (Static Random Access Memory), the program processing results are stored in the cell with volatile data.
In a power-off mode of the system, various data stored in a register are destroyed. As a result, since the program restarts from the initial stage although the power of the systems is restored, the efficiency for data storage is degraded, and power consumption is increased.
As the capability and the performance of the system becomes complicated and improved, the performance of system register files is required to be improved. Specifically, with the development of a superscalar structure and simultaneous/multiple/thread technologies, the embodiment of a multi port register for processing multiple data simultaneously is more required rather than a single port register.